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Xelerated (News - Alert), a provider of network processing and programmable Ethernet switching solutions, announced volume production of its HX family of 100G network processors (NPU) for packet-OTN, mobile backhaul/PTN and Carrier Ethernet Switch-Routers.

In a release, Anders Ericsson (News - Alert), Xelerated VP Sales and Marketing, said, “The high demand for the HX family of NPUs is due to its combination of low power consumption, programmable wirespeed processing and integration of advanced traffic management.”

“We are thrilled about some of our new customer projects now going into production. These platforms have the potential to reshape the Carrier Ethernet market,” Ericsson added.

It was revealed that the HX family of NPUs has been selected in 20 systems and plans are afoot to start manufacturing the first set this year itself. System vendors designing with Xelerated NPUs will be able to scale their systems besides meeting strict power budgets.

Also the HX family consumes 67 percent less power when compared to legacy NPUs, with respect to per processed gigabit of traffic.

As system vendors are required to provide new services and features to their Ethernet and IP/MPLS data planes and to increase feature velocity, data planes are implemented using network processors. These have been found to be flexible and can be further augmented using software upgrades.

Officials added that the HX family is designed for pizza box and line card slot capacities of 20-200 Gbps and they integrate inherent wirespeed processing and advanced traffic management along with deep packet buffering.

The HX NPU is capable of providing Ethernet/MPLS services for 100 Gbps of traffic via a single chip in the case of in packet-OTN systems. Specially designed for aggregation and transport these line cards also support a range of interface types including GE, 10GE, 40GE, 100GE and OTU0-OTU4. The HX family implements complete L2 and L3 switch-router applications for mobile backhaul.

The other features of the HX family of NPUs includes dataflow architecture featuring 448 PISC processor cores and 28 engine access points to connect to on-chip or off-chip table memory and hardware engines. It also features an advanced traffic manager with hierarchical per-user, per-service scheduling and shaping and deep off-chip packet buffer fully implemented in cost-effective DDR3 DRAM, added officials.