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Ethernet Extender - Avago Announces Vortex Gearbox Family of 28nm CMOS 100G Ethernet/OTN PHYs
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January 02, 2013

Avago Announces Vortex Gearbox Family of 28nm CMOS 100G Ethernet/OTN PHYs

TMCnet Contributor


 

Avago Technologies, which supplies analog interface components for wireless, wireline and industrial applications, has now jumped into the market for supplying physical layer transceiver (PHY) devices supporting Ethernet and Optical Transport Networking (OTN) with the release of its Vortex Gearbox line.


The Vortex Gearbox line features Avago’s 28nm CMOS SerDes technology that has demonstrated compliance with IEEE (News - Alert) CAUI and various Common Electrical Interface (CEI) standards that include CEI-11G-SR, CEI-25G-LR and CEI-28G-VSR, according to the company. The devices also include Avago’s proprietary Decision Feedback Equalization (DFE) architecture providing low overall power consumption, low data latency and jitter and crosstalk performance.

“The wired communications semiconductor market has become increasingly concentrated. On the basis of its proven SerDes technology and broad portfolio of ASICs, ASSPs, IP and optics, Avago enters the PHY ASSP market with instant credibility,” said Jag Bolaria in the Avago statement, senior analyst at The Linley Group.

The device is ideal for driving both backplane and portside applications, noted the company.

 “The features included in this first member of Avago’s new Vortex Gearbox family of customer channel products meet or exceed the requirements in both backplane and portside applications,” Bolaria agreed.

The first device released in the line is the Vortex Gearbox AVSP-1104, which is a single-chip PHY IC designed for high-density 100G Ethernet and OTN applications.

The AVSP-1104 features long reach performance withstanding up to 32dB of channel loss, as well as hole-free operation from 1-28 Gbps, according to the company.

It has functionality for full-duplex conversion of four lanes (4x25 Gbps, 4x28 Gbps) to ten lanes (10x10 Gbps, 10x11 Gbps), and an option for configuration as a retimer function for full-duplex transmission of 10 lanes.

The AVSP-1104 has programmable Tx/Rx equalization of all SerDes interfaces, and a Bit Error Rate (BER) of 1e-20.

It also comes with easy-to-use diagnostic software for remote debugging.

"With over 250 million SerDes channels shipped over the past decade, Avago has established a record of developing leading-edge embedded SerDes cores for high performance ASICs," said Frank Ostojic in a statement, vice president and general manager of Avago’s ASIC Products Division.

"Building on this foundation, we now offer the AVSP-1104, the first product in the Vortex Gearbox family,” he said. “We are delivering 100GbE solutions now and will enable designers to create systems incorporating serial communication at rates greater than 28Gbps in the near future.”

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Edited by Peter Bernstein
 

 
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