Cadence Design Systems (News - Alert) has announced the availability of Virtuoso Advanced Node, a new set of custom/analog capabilities designed specifically for the advanced technology nodes of 20 nanometers and below.
Pierre Dautriche, senior director at STMicroelectronics (News - Alert), said that their company has moved aggressively to meet the new complexities of 20-nanometer technology to stay on the cutting edge of design.
He said that the new Virtuoso advanced-node capabilities have provided high-quality automation for the custom/analog chips, contributing to the transition. “Virtuoso Advanced Node takes into account the idiosyncrasies of designing at 20 nanometers and ensures a much more efficient development cycle.”
Cadence has developed the new set of custom/analog capabilities on its Cadence Virtuoso custom/analog technology. Dr. Chi-Ping Hsu, senior vice president for Silicon Realization Group at Cadence, said that Virtuoso Advanced Node enables design teams to optimize their designs for performance, power and area while reducing or even eliminating tasks that would make 20-nanometer design much more time consuming and labor intensive.
With Virtuoso Advanced Node, engineers can develop their physical design and also simultaneously check it. Company officials said that this enables them to make sure that they are on the right track at each step of the designing cycle. Equipped with innovative capabilities, Virtuoso Advanced Node prevents errors before they are created rather than detect them late in the design process.
Moreover, the new offering provides designers the ability to use partially completed layout as part of the LDE analysis, which helps detect layout-dependent effects at the earliest moment in the design cycle. This helps decrease the cost of design iterations.
Additionally, Virtuoso Advanced Node helps develop complex mixed-signal chips, which are used to power consumer electronics devices. According to company officials, it enables the creation of area-optimization layout as it delivers real-time, automated color-aware, design-rule-driven layout.
Using this latest offering from Cadence, engineers can now match, lock and store colors on critical nets and geometries via schematic constraints or directly on the layout. They have the advantage of being able to identify, debug and fix error in the initial designing stage.
Earlier in December, Cadence launched Automotive Ethernet Design IP and Verification IP (VIP) for the latest Automotive Ethernet Controllers.
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Edited by Peter Bernstein