Now with the announcement of Westmere, Intel’s (News
architecture has the cost-conscious presence it needed to improve its popularity.
A bit of history: In September Intel released Lynnfield, the follow-up to its Nehalem architecture. Intel focused the launch campaign around the idea that Lynnfield was “Nehalem for the mainstream.”
It was a good choice. As BenchmarkReviews.com noted
, “Nehalem, for the first year of its life, was the only choice for those who wanted in on the company’s latest architecture, but thanks to the $300+ price tag (News
), many held off and waited for more budget-conscious models to come along.”
Not that there was anything horrendously wrong with Nehalem itself: Industry observer Mark Fontecchio wrote
last week that “it has been nearly a year since Intel released its first next-generation Xeon, or Nehalem, processors and end users are so happy with the result, they’re not chomping at the bit for the upcoming eight-core version.”
Then along came Westmere. A couple of weeks ago industry observer Ian Williams wrote
about upcoming series of Westmere processors, “the 32nm version of the Nehalem architecture, with chips dubbed Clarkdale for the desktop version and Arrandale for mobile.”
“As well as scaling down the die size,” Williams said, “Westmere offers a handful of new instructions, most of which center around AES mathematical operations in order to boost data encryption and decryption speeds.”
Lynnfield’s lowest-priced model, the Core i5-750, costs about $200. It doesn’t have HyperThreading, but other than that it’s pure Nehalem -- “in fact,” BenchmarkReviews says, “it even improved on certain aspects, such as with its more effective Turbo feature.”
Now with the coming of Westmere the Nehalem franchise gets a player with dual-core models set to sell for between $100 - $284, lowering the bar for pretty much anyone. BenchmarkReviews thinks the Westmere chips “share the equally-impressive Turbo multipliers of Lynnfield, along with the removal of the Northbridge,” and have “other benefits as well, such as HyperThreading, the AES-NI instruction set, and of course, improved power efficiency.”
David Sims is a contributing editor for TMCnet. To read more of David’s articles, please visit his columnist page. He also blogs for TMCnet here.
Edited by Marisa Torrieri