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Sequans Communications has achieved first-pass silicon success with its SQN1130 WiMAX (News - Alert) mobile station system-on-chip (SoC) by using Synopsys DesignWare USB 2.0 nanoPHY IP. The silicon-proven IP from Synopsys was selected after it met the area, power and performance requirements.

 

Sequans had to select an established USB IP provider since it was being faced by a critical time-to-market window. According to the director of ASIC design at Sequans Communications, Laurent Sibony, the company chose to rely on the standards-based IP expertise of Synopsys (News - Alert) in order to help meet its goals and achieve first-pass silicon success for its SQN1130 chip.

 

The SQN1130 from Sequans uses a MIMO algorithm of low-complexity to deliver high data throughput with low power consumption. In order to meet its low power and small area requirements, a USB 2.0 PHY core was required. After comparing with other IP offerings, Sequans chose the Synopsys DesignWare USB 2.0 nanoPHY IP since it was 30 percent lower in area and 15 percent lower in power.

 

Another important factor which led to the selection of Synopsys DesignWare USB IP is its tunability feature, according to the company. This feature allowed Sequans to maximize performance by enabling post-silicon adjustments quickly without having to modify their existing design. 

 

Documentation of Synopsys DesignWare USB 2.0 nanoPHY IP and access to its experienced technical team has enabled Sequans to reduce integration risk and speed up the time-to-market, according to the company. The silicon-proven IP has also enabled Sequans to achieve a yield that is greater than 99.7 percent.

 

According to John Koeter (News - Alert), the vice president of marketing for the Solutions Group at Synopsys, the company is focused on developing high-quality IP that is technically differentiated in terms of feature set, area and power which helps designers to reduce integration risk and meet their design requirements. The intellectual property and services from Synopsys address the challenges faced by designers and manufacturers like power and yield management, software-to-silicon verification and time-to-results.