Open-Silicon’s Interlaken IP core has been selected for deployment in Netronome’s (News - Alert) next-generation flow processors. The high-bandwidth Interlaken IP core is stated to have all the necessary features ideal for networking, security and content processing applications.
Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10 Gbps to 150 Gbps. The Interlaken specification minimizes the pin and power overhead of chip-to-chip interconnect, and features a flexible protocol layer that provides a scalable solution usable throughout an entire system.
The Open-Silicon Interlaken IP core can deliver the fastest chip-to-chip interface by supporting SerDes data rates up to 28Gbps and multiple data width options, and the SerDes PHYs’ support lets customers quickly integrate the core into any technology.
“Open-Silicon’s Interlaken IP core met the necessary requirements for Netronome’s next-generation flow processor and was easily integrated into our next-generation processor, even with the customization that we required,” noted Jim Finnegan, senior VP of Development at Netronome. “Open-Silicon’s support for our requirements and customizations has surpassed our expectations.”
Netronome’s sixth generation of flow processors reportedly packs 216 processing cores and 100 accelerators optimized for packet, flow, security and content processing in a single device. A series of patented architectural features, combined with the Intel (News - Alert) 22nm 3D Tri-Gate manufacturing process, results in the industry’s first programmable 200 Gbps flow processor.
These processors are stated to be suitable for 100-400 Gbps intelligent line cards, service blades and PCIe cards in applications such as carrier networking, cyber security, software-defined networking, mobile networking, virtualized data centers and cloud computing.
Open-Silicon added that working with Netronome on its next-generation flow processors applying advanced foundry technology has demonstrated the inherent capability and flexibility of its IP core.
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Edited by Braden Becker