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Cadence Intros Automotive Ethernet Design IP and VIP for Automotive Ethernet Controllers

December 27, 2012

Cadence Intros Automotive Ethernet Design IP and VIP for Automotive Ethernet Controllers

By Anil Sharma
TMCnet Contributor

Cadence Design Systems (News - Alert), Inc., a player in global electronic design innovation, has launched the industry’s first Automotive Ethernet Design IP and Verification IP (VIP) for the latest Automotive Ethernet Controllers.

“Car manufacturers are starting to deploy Automotive Ethernet over unshielded twisted pair cabling inside the vehicles. Therefore it is important for the industry that companies like Cadence provide Design and Verification IP that will enable the ecosystem to develop Ethernet-based products for in-vehicle communication,” said Ian Riches, director global automotive practice, at Strategy Analytics (News - Alert), in a statement.

Officials with Cadence Design Systems said that the Cadence MAC Design IP speeds development of automotive Ethernet-based integrated circuits.  Cadence Ethernet VIP customers can automate complex conformance tests of the Automotive Ethernet protocol and take advantage of advanced verification methodologies.  Additionally, Cadence VIP significantly shortens the overall test bench development time resulting in increased verification productivity.

“The introduction of Ethernet for in-vehicle networking delivers revolutionary benefits to automotive connectivity relative to the costly, low performance and proprietary technology previously used,” said Martin Lund, senior vice president, SOC Realization Group, Cadence.

“With our new IP and VIP offering, customers can more easily implement the latest automotive requirements and create advanced Ethernet-based products for in-vehicle communication,” said Lund.

Earlier in October, Cadence Design Systems had announced that TSMC has selected Cadence solutions for its 20-nanometer design infrastructure. The solutions cover the Virtuoso custom/analog and Encounter RTL-to-signoff platforms.

The TSMC 20-nanometer reference flows incorporate new features and methodologies in both Encounter and Virtuoso that take into account newly important wire characteristics, timing closure and design size considerations.

For the custom designer, Virtuoso technology supports new 20-nanometer constraints in the industry standard OpenAccess database, including G0 rules, interactive coloring for color-aware layout, a constraint-driven pre-coloring flow, odd-cycle loop prevention and detection, advanced Pcell abutment and support for local interconnect layers.

Cadence Integrated Physical Verification System is an in-design technology that integrates the Cadence Physical Verification System within the Virtuoso platform.

Want to learn more about the latest in communications and technology? Then be sure to attend ITEXPO Miami 2013, Jan 29- Feb. 1 in Miami, Florida.  Stay in touch with everything happening at ITEXPO (News - Alert). Follow us on Twitter.

Edited by Amanda Ciccatelli
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