TMCnet - World's Largest Communications and Technology Community



Cadence Design Systems Reduces Power Consumption for Yamaha
Green Technology Featured Articles
May 16, 2013

Cadence Design Systems Reduces Power Consumption for Yamaha

By Michael Guta
TMCnet Contributing Writer

Regulating power and maximizing the way in which it is used in modern devices is critical to the type of performance it delivers. Cadence Design Systems provides software, hardware, IP and services to design and verify advanced components. The company's solution for complex multi-bit cells is able to deliver power and performance benefits using the Virtuoso Liberate and Spectre tools to reduce power for mobile applications.

With the solutions from Virtuoso Liberate and Spectre, the company announced it has helped Yamaha (News - Alert) Corporation deliver a 10 percent reduction in dynamic power to the clock network required for Yamaha ASICs for its mobile consumer chips. The speedup turnaround time for characterization was also improved 2x compared to the technology Yamaha was using. The benefit of this performance from the chips will give Yamaha the ability to introduce these chips faster to the market.

"Cadence offered the only solution capable of characterizing our complex multi-bit cells. The Virtuoso Liberate and Spectre tools were critical in helping us develop our new low-power solution and in meeting our time to market goals," said Shuhei Ito, development director for the semiconductor division at Yamaha.

Virtuoso Liberate is an ultra-fast standard cell and I/O library characterization solution. It supports advanced timing, power, signal integrity DC current source models, Composite Current Source (News - Alert) (CCS) and Effective Current Source Models (ECSM). It allows automatic vector generation (AVG), and makes sure the characterizations of the library cells are complete, accurate and very efficient.

Virtuoso Spectre, on the flip side, is a circuit simulator that provides an accurate Simulation Program with Integrated Circuit Emphasis (SPICE)-level simulation for tough analog, radio frequency (RF) and mixed-signal circuits. The design gives it low memory consumption and high-capacity analysis in multiple domains.

"Yamaha's previous technology was unable to characterize the complex multi-bit flip-flop cells required for the low-power flow Yamaha adopted,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “With its patented 'Inside View' technology, the Virtuoso Liberate tools enabled Yamaha to characterize these cells automatically by eliminating the need for the user to define the functional description of the cell or specify worst-case conditions."

Edited by Alisen Downey

Green Technology Related Articles

Technology Marketing Corporation

35 Nutmeg Drive Suite 340, Trumbull, Connecticut 06611 USA
Ph: 800-243-6002, 203-852-6800
Fx: 203-866-3326

General comments:
Comments about this site:


© 2018 Technology Marketing Corporation. All rights reserved | Privacy Policy