TMCnews Featured Article

Officials at Hitachi, Ltd. say they’re now able to reduce printed circuit board place-and-route design time by nearly 40 percent – especially for a high-speed communication product by implementing Cadence Design Systems‘s Allegro Global Route Environment place-and-route design methodology.

 

According to Cadence, its GRE technology is an interconnect planning and routing technology designed for PCB, which provides users with automation for various stages of interconnect planning and routing where no automation was available earlier.

 

The GRE technology works in three phases. At the beginning of the process (first phase), it allows users to plan the routing strategy at a high-level via Interconnect Flow Designer. With the help of Interconnect Feasibility capability it checks and provides feedback on available space for each of the flows, allowing users to modify their routing strategy. It also determines the routing paths, net topologies and assigned electric constraints during the middle phase.

 

Cadence says that in the final planning phase, the GRE technology performs feasibility routing against the pre-determined routing flow, and then automatically completes routing. This approach is seen to be very effective for memory interfaces such as DDR2, DDR3, and serial interfaces such as PCI Express and PCI Express Gen II with their stringent high-speed design constraints.

 

AJ Incorvaia, vice president of research & development, Allegro - R&D Development at Cadence, said, “Cadence GRE technology is the next generation of PCB interconnect planning and routing technology. It offers automation for designs with high-speed interfaces such as DDR2, SATA, and PCI Express.”

 

Incorvaia added: “In order to design today’s PCBs with high-speed constraints while maintaining quality levels like those of Hitachi (News - Alert), it is imperative to make route strategy trade-offs at early stages of design as well as have a unified and global methodology for routing. By combining their high-level requirements PCB design with GRE technology, Hitachi is able to significantly shorten their overall PCB design cycle. This success will become a standard reference for a new design methodology for high-speed PCBs.”

 

Leveraging GRE technology, Hitachi Communication Technologies, Ltd., the communication products division of Hitachi Group, was able to streamline its PCB design process and thereby reported time-saving results as part of a companywide initiative to enhance design efficiency and reduce design-cycle time.

 

In addition, the GRE technology helps in improving the quality of PCB designs by enabling users to concurrently work on the placement and the exploration of the routing strategies and paths. This technology will also be effective for many other PCB design challenges, such as engineering changes and routing estimation.

 

Hitachi said that it has plans to deploy as well as promote the GRE technology as a standard solution throughout the design environment.

 

In 2007, Hitachi standardized on Cadence EDA products in order to enhance design efficiency as well as reduce the design-cycle time for company’s hardware products.