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Sierra Monolithics, a supplier of Analog and Mixed Signal IC solutions for Optical Communication, Wireless, and Microwave/Millimeter Wave applications, has just launched its 100G multiplexer with clock multiplier unit (CMU) and demultiplexer with clock and data recovery (CDR).

 

Sierra claims that this newly launched 100G multiplexer and demultiplexer are the world’s first such one available till date.

 

For nearly 20 years, Sierra Monolithics (News - Alert) has been specializing in designing high frequency communication components that offer high reliability and performance. According to the company, this recently launched devices are the key components for equipment used in both the short-reach data center and high-performance computing market, as well as long-haul and metro carrier networks that are carrying growing volumes of IPTV (News - Alert), Internet video, multimedia conferencing, HD programming, mobile video phones, on-line gaming, networked storage and other high-bandwidth transport payloads.

 

“Sierra Monolithics has built on the leadership foundation of our pioneering 40G family to deliver the industry’s first 100G MUX/CMU and CDR/DEMUX,” said Javed Patel, president and chief executive officer at Sierra Monolithics.

 

“This chipset will enable the development of 100G transponder modules and line cards that will relieve carriers’ increasingly congested network routes and significantly lower their transport costs per bit, while also increasing throughput in data center networks so they can support today’s exponentially growing demand for video, peer-to-peer and virtualization services,” added Patel.

 

Sierra Monolithics’s Theta-100G solution includes the SMI10021 10:4 MUX/CMU and SMI10031 4:10 CDR/DEMUX devices. Each of these devices uses the fourth-generation, 130-nanometer IBM (News - Alert) 8HP bipolar complementary metal-oxide semiconductor (BiCMOS) silicon germanium (SiGe) process technology, enabling the lowest possible size, cost and power consumption.

 

A single 100G wavelength delivers ten times the bandwidth of dense wavelength division multiplexing (DWDM) transport solutions, with a capability to support 800,000 simultaneous Internet calls. Apart from this, the 100G standards are also expected to provide a convergence point between transport and Ethernet networks.

 

The Theta-100G chipset features a 10x10.3Gb/s (MLD/CAUI) or 11x11.2Gb/s SFI-S interface on the client side, as well as a de-skew function in compliance with OIF (News - Alert) SFI.S, plus a line side pre-skew function for the MLD/CAUI interface with a depth of 84UI. The inclusion of on-chip, selectable single- and dual-DQPSK precoding circuitry delivers high spectral efficiency, high optical signal-to-noise ratio sensitivity, and robustness against dispersion.

 

Other features include on-chip industry-standard selectable phase detector on-chip dual-mode (PRWS) pattern generators and error checkers, and SPI control interfaces with clock rates to at least 150 MHz. Typical jitter swing is 3.7psec p-p typical, and the differential output level is 0.6 to 1.2V p-p.

 

Sierra mentioned that the shipment of this newly launched Theta-100G SMI10021 and SMI10031 devices will begin in second quarter 2009, and these devices are available in a surface mount BGA (Ball Grid Array) package.