Xilinx Provides High-Speed Transmission With New Integration
May 22, 2017
Faster speed is the one constant in IT, and as more consumers carry around the same computing power of desktops in their smartphones with them at all times, the pressure to deliver faster services is only going to increase. For telecoms, data centers, network operators and enterprises, it means leveraging technologies to get the most out of them until new solutions come online. Xilinx (News - Alert) is helping in this effort by integrating 56-Gbps PAM4 transceiver technology into its Virtex UltraScale+ FPGAs to deliver high-speed transmission in backplanes, optics, and high-performance interconnects.
Xilinx provides all-programmable semiconductor products, including FPGAs, SoCs, MPSoCs, RFSoCs, and 3D ICs for software defined and hardware optimized applications. These products power advancements in industrial IoT, embedded vision, 5G wireless and cloud computing.
Connected through programmable interconnects, Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs). They can be programmed after they have been manufactured with the desired application or functionality the customer requires. This type of flexibility gives service providers, telecoms and others a platform for adapting in today's digital ecosystem.
Xilinx said the integration of the 56-Gbps PAM4 (4-level Pulse (News - Alert) Amplitude Modulation) transceiver technology into its Virtex UltraScale+ FPGAs is going to give its Virtex platform the elasticity to be deployed in different types of designs that use PAM4 for high-speed transmission. This 56-Gbps PAM4 transceiver capability was demonstrated by the company on 16-nm programmable silicon last year. This year, Xilinx added the same feature on its Virtex UltraScale+ devices, which leverage a 16-nm FinFET+ FPGA fabric.
The integration of 56Gb/s transceivers into its 16nm FinFET+ Virtex UltraScale+ FPGA family is driving the next wave of Ethernet deployment with a new transceiver architecture that is breaking the physical limitations of data transmission at 50G+ line rates. It also minimizes channel loss with next generation equalization technologies while supporting chip-to-chip, module, direct-attach cable, and backplane communication.
“Xilinx is leading the charge on transceiver technology with the infusion of 56G PAM4 into our 16nm FPGAsThese new devices are built upon a proven FPGA foundation and are in alignment with the vast ecosystem of optics, ASICs, and backplanes soon to be deployed,” said Ken Chang, vice president, SerDes Technology Group at Xilinx.
The latest transceiver architecture will allow vendors to scale 50G, 100G, 400G ports, as well as terabit interfaces to address applications with high-speed transmission and bandwidth demands, including cloud computing, Industrial IoT, Software-Defined Networks (SDN), wired communications, data centers, wireless backhaul and more.
Edited by Alicia Young
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