Freescale Semiconductor Assigned Patent for Static Random Access Memory (SRAM) Having Bit Cells Accessible by Separate Read and Write Paths
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Jan. 4 -- Freescale Semiconductor, Austin, Texas, has been assigned a patent (8,345,469) developed by Perry H. Pelley, Austin, Texas, and Ravindraraj Ramaraju, Round Rock, Texas, for "static random access memory (SRAM) having bit cells accessible by separate read and write paths."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of inverters for storing a logic state, optimized for being written, and powered by a read voltage during a read of the first plurality of bit cells. Each bit cell of the first plurality of bit cells is coupled to a true read bit line and a true write bit line, and a second plurality of bit cells is coupled to a complementary read bit line and a complementary write bit line. The true and complementary read bit lines are precharged to a precharge voltage of about half the read voltage. The true read bit line is predisposed to a logic low condition. One of a group consisting of a high impedance from the first bit cell to indicate that the logic state is a logic low and a signal voltage greater than the intermediate voltage to indicate that the logic state is a logic high is output from the first bit cell to the true read bit line."
The patent application was filed on Sept. 16, 2010 (12/883,275). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,345,469&OS=8,345,469&RS=8,345,469
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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