GLO Assigned Patent for Coalesced Nanowire Structures with Interstitial Voids and Method fManufacturing the Same
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Jan. 15 -- GLO, Lund, Sweden, has been assigned a patent (8,350,249) developed by Patrik Svensson, Palo Alto, Calif., for a "coalesced nanowire structures with interstitial voids and method for manufacturing the same."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids."
The patent application was filed on Sept. 26, 2011 (13/245,405). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,350,249.PN.&OS=PN/8,350,249&RS=PN/8,350,249
Written by Kusum Sangma; edited by Anand Kumar.
(c) 2013 Targeted News Service
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