STATS ChipPAC Assigned Patent
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Jan. 15 -- STATS ChipPAC, Singapore, has been assigned a patent (8,350,384) developed by Rajendra D. Pendse, Fremont, Calif., for a "semiconductor device and method of forming electrical interconnect with stress relief void."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A semiconductor device has a semiconductor die with a plurality of tapered bumps formed over a surface of the semiconductor die. The tapered bumps can have a non-collapsible portion and collapsible portion. A plurality of conductive traces is formed over a substrate with interconnect sites. A masking layer is formed over the substrate with openings over the conductive traces. The tapered bumps are bonded to the interconnect sites so that the tapered bumps contact the mask layer and conductive traces to form a void within the opening of the mask layer over the substrate. The substrate can be non-wettable to aid with forming the void in the opening of the masking layer. The void provides thermally induced stress relief. Alternatively, the masking layer is sufficiently thin to avoid the tapered interconnect structures contacting the mask layer. An encapsulant or underfill material is deposited between the semiconductor die and substrate."
The patent application was filed on Dec. 9, 2010 (12/963,934). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,350,384.PN.&OS=PN/8,350,384&RS=PN/8,350,384
Written by Kusum Sangma; edited by Anand Kumar.
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