California Inventors Develop Patent for Reduced Mask Configuration for Power Mosfets with Electrostatic Discharge (ESD) Circuit Protection
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Jan. 22 -- Anup Bhalla, Santa Clara, Calif., Xiaobin Wang, San Jose, Calif., Wei Wang, Santa Clara, Calif., Yi Su, Sunnyvale, Calif., and Daniel Ng, Campbell, Calif., have developed a patent (8,354,316) for a "reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer."
The patent application was filed on Oct. 29, 2010 (12/925,820). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,354,316&OS=8,354,316&RS=8,354,316
Written by Arpi Sharma; edited by Anand Kumar.
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