Vishay-Siliconix Assigned Patent
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Feb. 9 -- Vishay-Siliconix, Santa Clara, Calif., has been assigned a patent (8,367,500) developed by Robert Q. Xu, Fremont, Calif., and Jacek Korec, San Jose, Calif., for a "method of forming self aligned contacts for a power MOSFET."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas."
The patent application was filed on March 3, 2003 (10/378,766). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,367,500&OS=8,367,500&RS=8,367,500
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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