|[February 20, 2013]
Blue Pearl Software Advances FPGA RTL Signoff, Announces Release 6.2 with Enhanced Grey Cell Methodology
SAN JOSE, Calif. --(Business Wire)--
Pearl Software, Inc., the provider of next generation EDA software
that increases designer productivity and design quality, announced that
it is shipping Release 6.2 of its Blue
Pearl Software Suite, for Windows and Linux operating systems. The
new version includes enhancements that improve and further accelerates
FPGA design verification, including one of its biggest design challenges
- chip-level clock domain crossing analysis.
"We are very pleased to see that the Blue Pearl Software Suite
integrates well with Xilinx's (News - Alert) latest solutions like Vivado™ Design Suite
and Zynq™-7000 All Programmable SoC," said Sanjay Gehani, Senior Manager
Alliance Program at Xilinx. "This addresses the growing verification
concerns of IP connectivity and rule compliance checking for complex
"Our collaboration with Xilinx resulted in an optimized flow for the
FPGA synthesis and place & route implementation flow," said Ellis Smith,
Chairman and CEO of Blue Pearl. "With our enhanced Grey Cell methodology
we are now enabling an industry-first chip-level clock-domain crossing
(CDC) solution at the RTL level."
What's New in 6.2
Enhancements to Blue Pearl Software Suite™ Version 6.2 inlude:
Enhanced analysis using a Grey Cell methodology
Better runtime due to enhanced connectivity and smaller database
Enhanced multi-cycle path analysis
Previous announcements included multi-language (SystemVerilog, VHDL, and
Verilog) support, mode-based path analysis, TCL tool control, a longest
path viewer and an improved FPGA synthesis flow.
To Learn More
Pearl Software Suite will be demonstrated at embedded world 2013,
Hall 4-615, NürnbergMesse, Nuremberg, Germany.
Please click on the following links to sign up for a hands-on
workshops and software
About Blue Pearl Software
Pearl Software, Inc. provides RTL Signoff software that uses new and
innovative technology to reduce design flow iterations and increase
designer productivity early in the digital design flow. By partnering
with key players of the FPGA Ecosystem, Blue Pearl Software accelerates
FPGA implementation. Blue
Pearl Software Suite checks RTL designs for functional errors and
automatically generates comprehensive and accurate Synopsys (News - Alert) Design
Constraints (SDC) to improve quality of results (QoR) and reduce FPGA
and ASIC design risks.
Visit Blue Pearl Software at http://www.bluepearlsoftware.com.
All trademarks are property of their respective owners.
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