U.S. Patents Awarded to Inventors in Vermont (Feb. 22)

(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., Feb. 22 -- The following federal patents were awarded to inventors in Vermont.

*** International Business Machines Assigned Patent for Chip Inductor with Frequency Dependent Inductance ALEXANDRIA, Va., Feb. 22 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,378,448) developed by Hanyi Ding, Colchester, Vt., and Wayne H. Woods Jr., Burlington, Vt., for a "chip inductor with frequency dependent inductance." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies." The patent application was filed on Dec. 7, 2009 (12/632,030). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,378,448&OS=8,378,448&RS=8,378,448 Written by Arpi Sharma; edited by Anand Kumar.

*** International Business Machines Assigned Patent for Interdigitated Vertical Parallel Capacitor ALEXANDRIA, Va., Feb. 22 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,378,450) developed by four co-inventors for an "interdigitated vertical parallel capacitor." The co-inventors are Roger A. Booth Jr., Hopewell Junction, N.Y., Douglas D. Coolbaugh, Hopewell Junction, N.Y., Ebenezer E. Eshun, Hopewell Junction, N.Y., and Zhong-Xiang He, Essex Junction, Vt.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor." The patent application was filed on Aug. 27, 2009 (12/548,484). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,378,450&OS=8,378,450&RS=8,378,450 Written by Arpi Sharma; edited by Anand Kumar.

*** International Business Machines Assigned Patent for Isolation FET for Integrated Circuit ALEXANDRIA, Va., Feb. 22 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,378,419) developed by Brent A. Anderson, Jericho, Vt., and Edward J. Nowak, Essex Junction, Vt., for an "isolation FET for integrated circuit." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An integrated circuit (IC) includes an active region; a pair of active field effect transistors (FETs) in the active region; and an isolation FET located between the pair of active FETs in the active region, the isolation FET configured to provide electrical isolation between the pair of active FETs, wherein the isolation FET has at least one different physical parameter or electrical parameter from the pair of active FETs." The patent application was filed on Nov. 22, 2010 (12/951,575). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,378,419&OS=8,378,419&RS=8,378,419 Written by Arpi Sharma; edited by Anand Kumar.

*** International Business Machines Assigned Patent for Method for Forming and Structure of a Recessed Source/Drain Strap for a MUGFET ALEXANDRIA, Va., Feb. 22 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,378,394) developed by four co-inventors for a "method for forming and structure of a recessed source/drain strap for a MUGFET." The co-inventors are Brent A. Anderson, Jericho, Vt., Andres Bryant, Burlington, Vt., Edward J. Nowak, Essex Junction, Vt., and Jed H. Rankin, Richmond, Vt.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer, relative to a bottom of the structure. Each of the fins comprises a central semiconductor portion and conductive end portions. At least one conductive strap may be positioned within the insulator layer below the fins, relative to the bottom of the structure. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap further includes recessed portions disposed within the insulator layer, below the plurality of fins, relative to the bottom of the structure, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins, relative to the bottom of the structure. The conductive strap is disposed in at least one of a source and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator." The patent application was filed on Sept. 7, 2010 (12/876,343). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,378,394&OS=8,378,394&RS=8,378,394 Written by Arpi Sharma; edited by Anand Kumar.

*** International Business Machines Assigned Patent for Utilization of Overvoltage and Overcurrent Compensation to Extend the Usable Operating Range of Electronic Devices ALEXANDRIA, Va., Feb. 22 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,378,271) developed by Gary E. O'Neil, Raleigh, N.C., Michael E. Stopford, Milton, Vt., and James B. Tate, Apex, N.C., for a "utilization of overvoltage and overcurrent compensation to extend the usable operating range of electronic devices." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and system for inducing augmented levels of heat dissipation by exploiting quiescent IC leakage currents to control the temperature in high power devices. A heat control and temperature monitoring system (HCTMS) utilizes a thermal sensor to sense the junction temperature of a component, which becomes self-heated due to the quiescent leakage current inherent to the component upon the application of power to the component. By increasing the voltage level of the power source, this quiescent self-heating property is augmented, which serves to accelerate the preheating of the device, until the temperature rises above the minimum specified operating temperature of the component. The system is then reliably initialized by applying full system power and triggering a defined initialization sequence/procedure. Once the component is operational, the component's temperature is maintained above the minimum operating threshold via continued self-heating, continued augmentation of the applied DC voltage, or both, as is required." The patent application was filed on July 11, 2007 (11/776,340). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,378,271&OS=8,378,271&RS=8,378,271 Written by Arpi Sharma; edited by Anand Kumar.

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