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University of California Assigned Patent
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., March 1 -- The University of California, Oakland, Calif., has been assigned a patent (8,384,122) developed by five co-inventors for a "tunneling transistor suitable for low voltage operation." The co-inventors are Chenming Hu, Oakland, Calif., Anupama Bowonder, Berkeley, Calif., Pratik Patel, Berkeley, Calif., Daniel Chou, Houston, and Prashant Majhi, Austin, Texas.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor."
The patent application was filed on April 17, 2009 (12/425,962). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,84,122.PN.&OS=PN/83,84,122&RS=PN/83,84,122
Written by Amal Ahmed; edited by Jaya Anand.
AM0301JA0301-848056
(c) 2013 Targeted News Service
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