National Semiconductor Assigned Patent
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., March 9 -- National Semiconductor, Santa Clara, Calif., has been assigned a patent (8,389,334) developed by Aninyda Poddar, Sunnyvale, Calif., Nghia T. Tu, San Jose, Calif., and Hau Nguyen, San Jose, Calif., for a "foil-based method for packaging intergrated circuits."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "One aspect of the present invention involves a foil-based method for packaging integrated circuits. Initially, a metallic foil and a photoresist layer are attached with a carrier. The photoresist layer is exposed and patterned. Afterward, multiple integrated circuit dice are connected to the foil. The dice and portions of the foil are encapsulated in a molding material. The foil is then etched based on the patterned photoresist layer to define multiple device areas in the foil, where each device area supports at least one of the integrated circuit dice. Some aspects of the present invention relate to panel arrangements that are involved in the aforementioned method."
The patent application was filed on Aug. 17, 2010 (12/858,331). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,389,334&OS=8,389,334&RS=8,389,334
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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