Intel Assigned Patent for Flexible Interconnect Pattern on Semiconductor Package
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Aug. 30 -- Intel, Santa Clara, Calif., has been assigned a patent (8,518,750) developed by four co-inventors for a "flexible interconnect pattern on semiconductor package." The co-inventors are Yoshihiro Tomita, Ibaraki-Ken, Japan, David Chau, Chandler, Ariz., Gregory M. Chrysler, Chandler, Ariz., and Devendra Natekar, Chandler, Ariz.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered."
The patent application was filed on Jan. 4, 2013 (13/734,861). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=85,18,750.PN.&OS=PN/85,18,750&RS=PN/85,18,750
Written by Amal Ahmed; edited by Jaya Anand.
(c) 2013 Targeted News Service
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