Intel Assigned Patent
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Aug. 31 -- Intel, Santa Clara, Calif., has been assigned a patent (8,519,510) developed by four co-inventors for a "semiconductor structure having an integrated quadruple-wall capacitor for embedded dynamic random access memory (eDRAM) and method to form the same." The co-inventors are Brian S. Doyle, Portland, Ore., Uday Shah, Portland, Ore., Satyarth Suri, Hillsboro, Ore., and Ramanan V. Chebiam, Hillsboro, Ore.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Semiconductor structures having integrated quadruple-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded quadruple-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A quadruple arrangement of metal plates is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the quadruple arrangement of metal plates. A top metal plate layer is disposed on and conformal with the second dielectric layer."
The patent application was filed on June 21, 2011 (13/165,615). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=85,19,510.PN.&OS=PN/85,19,510&RS=PN/85,19,510
Written by Deviprasad Jena; edited by Jaya Anand.
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