International Business Machines Assigned Patent for Synchronizing Global Clocks in 3d Stacks of Integrated Circuits by Shorting the Clock Network
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Sept. 7 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,525,569) developed by Thomas J. Bucelot, Wappingers Falls, N.Y., Liang-Teck Pang, White Plains, N.Y., and Phillip J. Restle, Katonah, N.Y., for "synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations."
The patent application was filed on Aug. 25, 2011 (13/217,335). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8525569.PN.&OS=PN/8525569&RS=PN/8525569
Written by Sudarshan Harpal; edited by Jaya Anand.
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