Georgia Tech Research Assigned Patent
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Sept. 21 -- Georgia Tech Research, Atlanta, has been assigned a patent (8,536,695) developed by four co-inventors for "chip-last embedded interconnect structures." The co-inventors are Fuhan Liu, Atlanta, Nitesh Kumbhat, Atlanta, Venkatesh Sundaram, Alpharetta, Ga., and Rao R. Tummala, Greensboro, Ga.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options."
The patent application was filed on March 8, 2012 (13/415,503). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8536695.PN.&OS=PN/8536695&RS=PN/8536695
Written by Deviprasad Jena; edited by Jaya Anand.
(c) 2013 Targeted News Service
[ Back To Technology News's Homepage ]