Cadence Design Systems Assigned Patent for Integrated Circuit Verification
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Oct. 18 -- Cadence Design Systems Inc., San Jose, Calif., has been assigned a patent (8,560,985) developed by four co-inventors for a method of performing "configuration-based merging of coverage data results for functional verification of integrated circuits." The co-inventors are Bijaya Sahu, Ghaziabad, India, Sandeep Pagey, Noida, India, Frank Armbruster, Erfurt, Germany, and Hannes Froehlich, East Sussex, United Kingdom.
The patent application was filed on Sept. 6, 2011 (13/226,481). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.htm&r=108&f=G&l=50&d=PTXT&s1=20131015.PD.&s2=%28CA.ASST.%29&co1=AND&p=3&OS=ISD/10/15/2013+AND+AS/CA&RS=ISD/10/15/2013+AND+AS/CA
Written by Jude Bautista; edited by Marlyn Vitin.
(c) 2013 Targeted News Service
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