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TMCNet:  Leti Announces Update of UTSOI Model that Allows Designers To Improve Trade-Off between Performance and Power Use

[December 07, 2013]

Leti Announces Update of UTSOI Model that Allows Designers To Improve Trade-Off between Performance and Power Use

GRENOBLE, France --(Business Wire)--

CEA-Leti announced today that Leti-UTSOI2, the first complete compact model that enlarges the physically described bias range for designers, is available in all major SPICE simulators.

The updated model, which can account for back interface inversion in ultra-thin body & box (UTBB) transistors, maintains a formal symmetry between front and back interface in all equations of the core model. It also includes a full description of the creation of an inversion layer at the rear face of the silicon film. This physical description is based on an original and non-simplified resolution of the equations that govern the electrostatics of the transistor.

The updated model, which will be presented during Session 12, Dec. 10, at IEDM 2013 in Washington, D.C., is the first compact model exhibiting this capability. It also can describe transistor behaviors in a large range of polarization applied both at the front and at the rear interface of the transistor.

"Enlarging the back biasing range accessible to the design community is key to optimizing the trade-off between performance and power consumption for UTBB technology," said Thierry Poiroux, research engineer at Leti and model co-developer. "This provides more opportunities to utilize FDSOI's advantages for mobile devicesand other applications that require efficient energy use."

FDSOI exhibits several major advantages for advanced technology nodes. It allows an electrostatic control by the gate on the channel of the transistor that is significantly better than conventional architectures. This control improves the trade-off between performance and power consumption at the circuit level, and enables significant improvements in silicon chip miniaturization.

In addition, FDSOI is a planar technology, which makes the transition from conventional technologies easier, and allows significantly simplified manufacturability compared to FinFET technology.

The Leti-UTSOI2 compact model was developed to describe the electrical behavior of FDSOI transistors by taking into account all their specificities. The model is based on a physical description of the device and all the parameters are physically based, which also allows its use for predictive analysis of the process.

The electrostatic coupling between the front and rear interfaces of the thin silicon film is part of the model. As a result it is particularly adapted to represent the behavior of the devices in low-doped, thin-silicon technologies in insulator layers ranging in thickness from nanometers to hundreds of micrometers.

The first version of Leti-UTSOI, valid for low-to-moderate back bias (up to Vdd), has already been implemented. It is available in major SPICE simulators (Agilent, Cadence, Mentor Graphics (News - Alert) and Synopsys) and it is also available in industrial process-design kits through the CMP. Online documentation and model cards (typical cases) are available at For access to the Verilog-A code, contact Leti.

The model's development was supported by STMicroelectronics (News - Alert) and partly funded by the ENIAC JU Places2Be project.

About CEA-Leti

By creating innovation and transferring it to industry, Leti is the bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. Backed by its portfolio of 2,200 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched more than 50 startups. Its 8,000m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices.

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