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TMCNet:  Research and Markets: The Multi-Component IC Packaging Market 2014 Edition

[February 25, 2014]

Research and Markets: The Multi-Component IC Packaging Market 2014 Edition

DUBLIN --(Business Wire)--

Research and Markets (http://www.researchandmarkets.com/research/nm5tf6/the) has announced the addition of the "The Multi-Component IC Packaging Market 2014 Edition" report to their offering.

Complex multi-component packages have added a new dimension to high speed and small form factor, and have been game changers for the industry. It is the package of the integrated circuit (IC) which holds the footprint to the printed circuit board (PCB), and thus it is the IC package which has enabled the multitude of small, handheld electronics to be invented and proliferate in today's world.

It is not just small size, but the added performance with high speed, more functionality, and the ability for handheld electronics to communicate via the Internet so that anyone with a smart phone or tablet has a wealth of information at their fingertips.

The costs per transistor is now going up with advancing technology nodes of 22nm and 14nm, when traditionally the cost goes down. Increasingly the backend, or IC packaging, is being looked at a meeting the needs of tomorrow's technology demands rather than the front end manufacturing.

Key Topics Covered:

Chapter 1: Introduction

1.1 Background

12 Scope


1.3 Organization

1.4 Methodology

Chapter 2: Executive Summary

2.1 Overview

2.2 Stacked Packages

2.3 Through-Vias Technology, 2-5D, and 3-D Interconnection Solutions

2.4 System in Package

Chapter 3: Stacked Packages

3.1 Overview

3.2 Types of Stacked Packages

3.3 The Ins and Outs of Stacked Packages

3.4 Interconnection

3.5 Stacked Package as a Multi-Component Package

3.6 Wafer Thinning

3.7 End Markets and Application Trends

3.8 New Product Introductions

3.9 Unit and Revenue Forecasts

Chapter 4: Through Vias, 3-D and 2.5-D Integration

4.1 Through Vias and 3-D Overview

4.2 2.5-D

4.3 2.5-D Interposers and Microbumps

4.4 Wide I/O

4.5 Creating the Vias

4.6 Who Takes Ownership of each Process Steps?

4.7 What does it Cost to Create 2.5-D and 3-D Devices

4.8 Issues / Solutions / Call to Action

4.9 3-D Die-Stacking Technology Requirements

4.10 Bonding Methods

4.11 Via First, Middle, or Last Technology

4.12 Via Etching and Filling

4.13 New Product/Process Highlights

4.14 Industry Consortiums

4.15 Market Potential

4.16 Future Markets

4.17 TSV Forecasts (2.5-D, 3-D, Interposer)

Chapter 5: System in Package

5.1 Overview

5.2 Hybrid Memory Cube

5.3 New Product Introductions/Highlights

5.5 SiP Forecasts

Companies Mentioned

- 3D Glass Solutions

- APSTL, llc

- Auburn University

- CEA-Leti

- Cisco, Inc. and Amkor (News - Alert) Technology

- Corning, Inc. Dow Chemical

- EV Group

- Fraunhofer Institute for Reliability and Microintegration

- Fujikura Ltd. (News - Alert) and FlipChip International, LLC

- Innovative Micro Technology

- Kyocera America

- Nanyang Technology University

- Sandia National Laboratories

- SET North America and RTI International CMET

- Shinko Electric Industries

- STATS ChipPAC Ltd. (News - Alert)

- SUNY College, College of Nanoscale Science and Engineering

- SUSS MicroTec

- Texas Instruments

- Tohoku University

- Triton Micro Technologies, Inc. and nMode Solutions

- Unimicron Technology Corporation and ITRI

For more information visit http://www.researchandmarkets.com/research/nm5tf6/the


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