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TMCNet:  U.S. Patents Awarded to Inventors in Idaho (May 12)

[May 12, 2014]

U.S. Patents Awarded to Inventors in Idaho (May 12)

(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., May 12 -- The following federal patents were awarded to inventors in Idaho.

*** Rambus Assigned Patent ALEXANDRIA, Va., May 12 -- Rambus, Sunnyvale, California, has been assigned a patent (8,717,052) developed by four co-inventors for a "testing fuse configurations in semiconductor devices." The co-inventors are Adrian E. Ong, Pleasanton, California, Paul Fuller, Ketchum, Idaho, Nick van Heel, Eagle, Idaho, and Mark Thomann, Boise, Idaho.


The patent application was filed on Aug. 9, 2011 (13/206,434). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,717,052.PN.&OS=PN/8,717,052&RS=PN/8,717,052 Written by Deviprasad Jena; edited by Jaya Anand.

*** Micron Technology Assigned Patent for Forming DRAM Array of Devices ALEXANDRIA, Va., May 12 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,716,116) developed by five co-inventors for a method "of forming a DRAM array of devices with vertically integrated recessed access device and digitline." The co-inventors are Kunal Parekh, Boise, Idaho, Ceredig Roberts, Boise, Idaho, Thy Tran, Boise, Idaho, Jim Jozwiak, Boise, Idaho, and David Hwang, Boise, Idaho.

The patent application was filed on March 10, 2010 (12/721,373). The full text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8716116.PN.&OS=PN/8716116&RS=PN/8716116 Written by Eloisa Asedillo; edited by Vessie Ann Abalos.

*** Micron Technology Assigned Patent for Variable Resistance Memory Device ALEXANDRIA, Va., May 12 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,717,799) developed by Jun Liu, Boise, Idaho, for a "variable resistance memory device with an interfacial adhesion heating layer, systems using the same and methods of forming the same." The patent application was filed on Aug. 16, 2012 (13/587,465). The full text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8717799.PN.&OS=PN/8717799&RS=PN/8717799 Written by Eloisa Asedillo; edited by Vessie Ann Abalos.

*** Micron Technology Assigned Patent for DRAM Cell Design ALEXANDRIA, Va., May 12 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,716,772) developed by two co-inventors for "DRAM cell design with folded digitline sense amplifier." The co-inventors are Fei Wang, Boise, Idaho, and Anton P. Eppich, Boise, Idaho.

The patent application was filed on Dec. 28, 2005 (11/320,376). The full text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8716772.PN.&OS=PN/8716772&RS=PN/8716772 Written by Eloisa Asedillo; edited by Vessie Ann Abalos.

*** Micron Technology Assigned Patent for Memory Array with Air Gap Between Memory Cells ALEXANDRIA, Va., May 12 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,716,084) developed by two co-inventors for a "memory array with an air gap between memory cells and the formation thereof." The co-inventors are Christopher J. Larsen, Boise, Idaho, and Andrew Bicksler, Nampa, Idaho.

The patent application was filed on May 24, 2013 (13/902,052). The full text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8716084.PN.&OS=PN/8716084&RS=PN/8716084 Written by Eloisa Asedillo; edited by Vessie Ann Abalos.

*** Micron Technology Assigned Patent for Quantizing Signals ALEXANDRIA, Va., May 12 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,717,220) developed by R. Jacob Baker, Boise, Idaho, for methods "of quantizing signals using variable reference signals." The patent application was filed on Nov. 29, 2011 (13/306,868). The full text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8717220.PN.&OS=PN/8717220&RS=PN/8717220 Written by Eloisa Asedillo; edited by Vessie Ann Abalos.

*** Micron Technology Assigned Patent for Semiconductor Device Stiffening Elements ALEXANDRIA, Va., May 12 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,716,849) developed by two co-inventors for a "semiconductor device including one or more stiffening elements." The co-inventors are Chad A. Cobbley, Boise, Idaho, and Cary J. Baerlocher, Meridian, Idaho.

The patent application was filed on April 3, 2012 (13/438,306). The full text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8716849.PN.&OS=PN/8716849&RS=PN/8716849 Written by Eloisa Asedillo; edited by Vessie Ann Abalos.

*** Micron Technology Assigned Patent for Floating Body Field-Effect Transistors ALEXANDRIA, Va., May 12 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,716,075) developed by five co-inventors for "floating body field-effect transistors, and methods of forming floating body field-effect transistors." The co-inventors are Di Li, Highland, California, Jun Liu, Boise, Idaho, Michael P. Violette, Boise, Idaho, Chandra Mouli, Boise, Idaho, and Howard Kirsch, Eagle, Idaho.

The patent application was filed on Feb. 7, 2013 (13/761,587). The full text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8716075.PN.&OS=PN/8716075&RS=PN/8716075 Written by Eloisa Asedillo; edited by Vessie Ann Abalos.

*** Micron Technology Assigned Patent for Reduced Cross Current Voltage Generators ALEXANDRIA, Va., May 12 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,716,897) developed by Dong Pan, Boise, Idaho, for "voltage generators having reduced or eliminated cross current." The patent application was filed on Jan. 31, 2011 (13/017,960). The full text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8716897.PN.&OS=PN/8716897&RS=PN/8716897 Written by Eloisa Asedillo; edited by Vessie Ann Abalos.

*** Micron Technology Assigned Patent for Forming Transistor Gates ALEXANDRIA, Va., May 12 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,716,119) developed by Yongjun Jeff Hu, Boise, Idaho, for methods "for forming transistor gates." The patent application was filed on Sept. 6, 2012 (13/605,848). The full text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8716119.PN.&OS=PN/8716119&RS=PN/8716119 Written by Eloisa Asedillo; edited by Vessie Ann Abalos.

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