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TMCNet:  Cadence Design Systems Assigned Patent for Method, System, and Computer Program Product for Preparing Multiple Layers of Semiconductor Substrates for...

[July 08, 2014]

Cadence Design Systems Assigned Patent for Method, System, and Computer Program Product for Preparing Multiple Layers of Semiconductor Substrates for...

(Targeted News Service Via Acquire Media NewsEdge) Cadence Design Systems Assigned Patent for Method, System, and Computer Program Product for Preparing Multiple Layers of Semiconductor Substrates for Electronic Designs By Targeted News Service ALEXANDRIA, Va., July 8 -- Cadence Design Systems, San Jose, California, has been assigned a patent (8,769,453) developed by Louis K. Scheffer, Campbell, California, and David White, San Jose, California, for a "method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs." The patent application was filed on Oct. 29, 2010 (12/916,469). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=87,69,453.PN.&OS=PN/87,69,453&RS=PN/87,69,453 Written by Sudarshan Harpal; edited by Jaya Anand.


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