[September 30, 2014] |
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Rambus to Showcase Security and Memory IP Core Solutions at ARM TechCon 2014
SANTA CLARA, Calif. --(Business Wire)--
Rambus (News - Alert) Inc. (NASDAQ:RMBS):
Who:
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Rambus (NASDAQ:RMBS)
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Where:
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ARM (News - Alert) TechCon 2014
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Santa Clara Convention Center - Booth #206
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5001 Great America Parkway, Santa Clara, Calif.
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armtechcon.com
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When:
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October 1-3, 2014
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At ARM TechCon 2014, Rambus will demonstrate its IP core innovations
across both memory and security technologies, including its Beyond
DDR4 initiative for next-generation
server applications and R+™
LPDDR3 for mobile applications. The
Rambus Cryptography Research Division will demonstrate the recently
launched Differential
Power Analysis (DPA) resistant cores, as well as the CryptoFirewall™
content protection core.
Demonstrations will be available at the Rambus booth, #206.
Demonstrations:
R+ LPDDR3 Fully compliant with LPDDR2 and LPDDR3, the R+™
LPDDR3 PHY is part of a complete memory solution designed for the latest
generation of mobile devices. When combined with R+ LPDDR3 DRAM, the R+
LPDDR3 memory solution reduces memory system power by up to 25%. This
demonstration will show a side-by-side silicon signaling comparison
between the R+ LPDDR3 PHY in standard and R+ low-swing signaling modes,
highlighting the power advantages delivered by the R+ architecture.
Beyond DDR4 - R+ Technology for Next-generation Server Memory This
demonstration will showcase next-generation technologies that extend
server memory solutions beyond the capabilities of DDR4. With data rates
of up to 6.4 Gbps in a multi-rank, multi-DIMM system, this
high-performance, high-capacity technology simplifies system design and
significantly reduces overall system power requirements.
DPA Resistant Cores As part of the family of DPA resistant
cryptographic cores from the Rambus Cryptography Research division, this
demonstration will showcase the side channel resistance of Rambus
high-performance AES cryptographic cores and libraries compared to
standard, unprotected AES implementations.
CryptoFirewall Security Core This demonstration
features a CryptoFirewall core implemented in an STMicroelectronics (News - Alert) (ST)
set-top-box (STB) chipset and development board. The chipset is
decrypting a video stream using the CryptoFirewall core to provide the
encryption key. Supported features include differentiation, provisioning
of rights using ERKs, channel change, and decryption of two streams
simultaneously with both displayed via picture-in-picture.
About Rambus Inc.
Rambus brings invention to market. Our customizable IP cores,
architecture licenses, tools, services, and training improve the
competitive advantage of our customer's products while accelerating
their time-to-market. Rambus products and innovations capture, secure
and move data. For more information, visit rambus.com.
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