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eSilicon to present power optimization paper at SNUG Singapore, September 21, 2018SAN JOSE, Calif., Sept. 17, 2018 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will present Power Optimization for ASICs: Using Custom Low-Power Flops, September 21 at SNUG Singapore. What EDA tools are shifting towards optimization of dynamic power from the well-established leakage power optimization, but that is not enough to compensate for the trend and it is necessary to look for additional design methods to reduce chip power consumption. Based on our designs we see that clock networks and, in particular, the power consumption of the flops is responsible for roughly 50 percent of total power consumption. For that reason, we have developed custom low-power flops to reduce overall chip power. These flops have been optimized for low power while still retaining good performance. However, since they re slower than performance-optimized flops it is necessary to use them properly to meet the performance requirements of high-performance chips. In this paper we present a methodology to make optimal use of our low-power flops without compromising the design performance using IC Compiler II. Using proprietary flops and the methodology presented here we can reduce power by around 15 percent without degrading the design performance. Who When Where About SNUG About eSilicon Collaborate. Differentiate. Win.™ eSilicon is a registered trademark, and the eSilicon logo and “Collaborate. Differentiate. Win.” are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.
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