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TMCNet:  U.S. Patents Awarded to Inventors in Oregon (Nov. 21)

[November 21, 2012]

U.S. Patents Awarded to Inventors in Oregon (Nov. 21)

(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., Nov. 21 -- The following federal patents were awarded to inventors in Oregon.

*** News Technologies Assigned Patent ALEXANDRIA, Va., Nov. 21 -- News Technologies, Lake Oswego, Ore., has been assigned a patent (8,315,932) developed by Steven A. Burrows, Lake Oswego, Ore., and John Elliott, Wilsonville, Ore., for "news induced automated electronic securities transactions." The abstract of the patent published by the U.S. Patent and Trademark Office states: "News information is received. It is determined if the news information contains a reference to a company. It is further determined if the news information matches criteria associated with the company. Securities are automatically trade upon determining that said news information contains a reference to the company and determining that said news information matches criteria associated with the company." The patent application was filed on June 30, 2011 (13/174,581). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,315,932&OS=8,315,932&RS=8,315,932 Written by Neha Bharti; edited by Jaya Anand.


*** Intel Assigned Patent ALEXANDRIA, Va., Nov. 21 -- Intel, Santa Clara, Calif., has been assigned a patent (8,316,414) developed by five co-inventors for a "reconfiguring a secure system." The co-inventors are Sham M. Datta, Hillsboro, Ore., Mohan J. Kumar, Aloha, Ore., James A. Sutton, Portland, Ore., Ernie Brickell, Portland, Ore., and Ioannis T. Schoinas, Portland, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock." The patent application was filed on Dec. 29, 2006 (11/618,649). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,316,414&OS=8,316,414&RS=8,316,414 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Cadence Design Systems Assigned Patent for Method and Mechanism for Implementing Extraction for an Integrated Circuit Design ALEXANDRIA, Va., Nov. 21 -- Cadence Design Systems, San Jose, Calif., has been assigned a patent (8,316,331) developed by four co-inventors for a "method and mechanism for implementing extraction for an integrated circuit design." The co-inventors are Eric Nequist, Monte Sereno, Calif., Richard Brashears, San Jose, Calif., Matthew A. Liberty, Lake Oswego, Ore., and Michael McSherry C. McSherry, Portland, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "An improved method and system for stitching one or more islands of an integrated circuit design is disclosed. Multiple connected island objects in the IC design are first identified. At least one of the multiple identified connected island objects is then modified to form a modified island object. The modified island object may then be stitched into the multiple identified connected island objects. In some embodiments, stitching a modified island object may be implemented by tracking the endpoint(s), port(s), or node(s) of the connected island object being modified and stitched." The patent application was filed on Jan. 7, 2011 (12/987,072). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,316,331&OS=8,316,331&RS=8,316,331 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Honeywell International Assigned Patent for Safe Partition scheduling on Multi-core Processors ALEXANDRIA, Va., Nov. 21 -- Honeywell International, Morristown, N.J., has been assigned a patent (8,316,368) developed by four co-inventors for "safe partition scheduling on multi-core processors." The co-inventors are Stephen C. Vestal, North Oaks, Minn., Pamela Binns, St. Paul, Minn., Aaron Larson, Shoreview, Minn., Murali Rangarajan, Plymouth, Minn., and Ryan Roffelsen, Tigard, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "One example is directed to a method of generating a set of schedules for use by a partitioning kernel to execute a plurality of partitions on a plurality of processor cores included in a multi-core processor unit. The method includes determining a duration to execute each of the plurality of partitions without interference and generating a candidate set of schedules using the respective duration for each of the plurality of partitions. The method further includes estimating how much interference occurs for each partition when the partitions are executed on the multi-core processor unit using the candidate set of schedules and generating a final set of schedules by, for at least one of the partitions, scaling the respective duration in order to account for the interference for that partition. The method further includes configuring the multi-core processor unit to use the final set of schedules to control the execution of the partitions using at least two of the cores." The patent application was filed on Feb. 5, 2009 (12/366,369). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,316,368&OS=8,316,368&RS=8,316,368 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Intel Assigned Patent for Generating Multiple Address Space Identifiers Per Virtual Machine to Switch between Protected Micro-contexts ALEXANDRIA, Va., Nov. 21 -- Intel, Santa Clara, Calif., has been assigned a patent (8,316,211) developed by four co-inventors for "generating multiple address space identifiers per virtual machine to switch between protected micro-contexts." The co-inventors are Uday Savagaonkar, Portland, Ore., Madhavan Parthasarathy, Portland, Ore., Ravi Sahita, Beaverton, Ore., and David Durham, Beaverton, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, an apparatus includes privileged mode logic, an interface, and memory management logic. The privileged mode logic is to transfer control of the processor among a plurality of virtual machines. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address. The determination logic is to determine whether an entry is storing an address of a different data structure for the first translation stage. The translation lookaside buffer is to store translations. Each translation lookaside buffer entry includes an address source identifiers. Each address source identifier is to identify a unique micro-context. Each address source identifier is based on a virtual partition identifier. At least two of the of virtual partition identifiers are associated with one of the virtual machines." The patent application was filed on June 30, 2008 (12/165,640). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,16,211.PN.&OS=PN/83,16,211&RS=PN/83,16,211 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for NAND Power Fail Recovery ALEXANDRIA, Va., Nov. 21 -- Intel, Santa Clara, Calif., has been assigned a patent (8,316,257) developed by four co-inventors for a "NAND power fail recovery." The co-inventors are Robert Royer, Portland, Ore., Sanjeev N. Trika, Hillsboro, Ore., Rick Coulson, Portland, Ore., and Robert W. Faber, Hillsboro, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed." The patent application was filed on April 13, 2011 (13/086,237). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,316,257.PN.&OS=PN/8,316,257&RS=PN/8,316,257 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Method and Apparatus for User-activity-based Dynamic Power Management and Policy Creation for Mobile Platforms ALEXANDRIA, Va., Nov. 21 -- Intel, Santa Clara, Calif., has been assigned a patent (8,316,247) developed by six co-inventors for a "method and apparatus for user-activity-based dynamic power management and policy creation for mobile platforms." The co-inventors are Georgios N. Theocharous, San Jose, Calif., Nilesh N. Shah, Rancho Cordova, Calif., Uttam K. Sengupta, Portland, Ore., William N. Schilit, Menlo Park, Calif., Kelan C. Silvester, Forest Grove, Ore., and Robert A. Dunstan, Portland, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and apparatus for user activity-based dynamic power management and policy creation for mobile platforms are described. In one embodiment, the method includes the monitoring of one or more sensor values of a mobile platform device to gather sensor activity data. Once the sensor activity data is gathered, the user state may be predicted according to the gathered user activity and an updated user state model. In one embodiment, the user state model is updated according to the sensor activity data. In one embodiment, a switch occurs from the present power management policy to a new power management policy if the new user state differs from a present user state by a predetermined amount. In one embodiment, at least one time-out parameter of a selected power management policy may be adjusted to comply with a predicted user state. Other embodiments are described and claimed." The patent application was filed on Dec. 17, 2010 (12/971,947). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,316,247.PN.&OS=PN/8,316,247&RS=PN/8,316,247 Written by Kusum Sangma; edited by Anand Kumar.

*** Cisco Technology Assigned Patent ALEXANDRIA, Va., Nov. 21 -- Cisco Technology, San Jose, Calif., has been assigned a patent (8,316,236) developed by David McGrew, Poolesville, Md., and Mark Baugher, Portland, Ore., for "determining security states using binary output sequences." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system for determining security associations using binary output sequences is described. In an example systematic embodiment, a first device is coupled over a network to a second device. Each device includes a processor and an indicator mechanism coupled to the processor. The indicator mechanism is configured to output a binary representation of a security state established between the devices to a user in perceivable proximity to at least one of the devices. A computer readable storage medium is coupled to the processor and includes executable instructions for the processor. The instructions when executed by the processor initiate a security transaction between the devices. The security transaction includes a protocol that uses one or more public keys to establish a security state between the devices. The indicator mechanism then outputs the binary representation to the user based on the established security state." The patent application was filed on Aug. 31, 2007 (11/848,582). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,16,236.PN.&OS=PN/83,16,236&RS=PN/83,16,236 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Method, System, and Apparatus for Dynamically Distributing a Computational Load between Clusters of Cores at a Frequency Greater than a Thermal Time Constant ALEXANDRIA, Va., Nov. 21 -- Intel, Santa Clara, Calif., has been assigned a patent (8,316,250) developed by Mark A. Trautman, Aloha, Ore., and Muralidhar Tirumala, Beaverton, Ore., for a "method, system, and apparatus for dynamically distributing a computational load between clusters of cores at a frequency greater than a thermal time constant." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method, apparatus, article of manufacture, and system, the method including, in some embodiments, processing a computational load by a first core of a multi-core processor, and dynamically distributing at least a portion of the computational load to a second core of the multi-core processor to reduce a power density of the multi-core processor for the processing of the computational load." The patent application was filed on Nov. 23, 2009 (12/592,302). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,316,250.PN.&OS=PN/8,316,250&RS=PN/8,316,250 Written by Kusum Sangma; edited by Anand Kumar.

*** Digimarc Assigned Paten ALEXANDRIA, Va., Nov. 21 -- Digimarc, Beaverton, Ore., has been assigned a patent (8,316,239) developed by Tyler J. McKinley, West Linn, Ore., and Ravi K. Sharma, Portland, Ore., for "decoding information to allow access to computerized systems." The abstract of the patent published by the U.S. Patent and Trademark Office states: "The presently claimed invention relates generally to gaining access to secure systems. One claim recites an apparatus including: an image or video sensor for capturing image or video data; and a multi-purpose computer processor configured to: decode machine-readable information encoded in captured image or video data representing a plurality of physical objects, each instance of machine-readable information includes identifying information; determine an order in which the physical objects are presented to the image or video sensor for evaluation via the identifying information; and comparing the order to a predetermined sequence to determine whether to allow access to a remotely located computerized system. The apparatus may be housed, e.g., in a cell phone. Other combinations and claims are provided as well." The patent application was filed on March 10, 2009 (12/401,394). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,316,239.PN.&OS=PN/8,316,239&RS=PN/8,316,239 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Domain-based Cache Management, Including Domain Event Based Priority Demotion ALEXANDRIA, Va., Nov. 21 -- Intel, Santa Clara, Calif., has been assigned a patent (8,316,184) developed by four co-inventors for a "domain-based cache management, including domain event based priority demotion." The co-inventors are Zhen Fang, Portland, Ore., Erik G. Hallnor, Beaverton, Ore., Nitin B. Gupte, Beaverton, Ore., and Steven Zhang, Hillsboro, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Domain-based cache management methods and systems, including domain event based priority demotion ("EPD"). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such as upon encoding of one or more macroblocks of a video frame. New data blocks may be written over lowest priority cached data blocks. New data blocks may initially be assigned a highest priority. Alternatively, or additionally, one or more new data blocks may initially be assigned one of a plurality of higher priorities based on domain-based information, such as a relative position of a requested data block within a video frame, and/or a relative direction associated with a requested data block. Domain-based cache management may be implemented with one or more other cache management techniques, such as least recently used techniques. Domain-based cache management may be implemented in associative caches, including set associative caches and fully associative caches, and may be implemented with indirect indexing." The patent application was filed on June 30, 2008 (12/165,350). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,16,184.PN.&OS=PN/83,16,184&RS=PN/83,16,184 Written by Kusum Sangma; edited by Anand Kumar.

*** Mentor Graphics Assigned Patent ALEXANDRIA, Va., Nov. 21 -- Mentor Graphics, Wilsonville, Ore., has been assigned a patent (8,316,265) developed by Ruifeng Guo, Portland, Ore., Wu-Tung Cheng, Lake Oswego, Ore., and Yu Huang, Sudbury, Mass., for a "test pattern generation for diagnosing scan chain failures." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of the disclosed technology comprise techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. At least some embodiments can be used to locate faults over multiple capture cycles in the scan chain." The patent application was filed on May 22, 2009 (12/471,227). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,316,265.PN.&OS=PN/8,316,265&RS=PN/8,316,265 Written by Kusum Sangma; edited by Anand Kumar.

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