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100 GbE CMOS SerDes Architecture Announced by Inphi
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Smart Data Centers Feature Editorial


March 14, 2011

100 GbE CMOS SerDes Architecture Announced by Inphi

By Calvin Azuri, TMCnet Contributor


A new 100 GbE CMOS SerDes architecture called iPHY has been announced by Inphi Corporation, a top provider of high-speed analog semiconductor solutions for the communications and computing markets. Next generation low power and high port density will now be easy to develop with iPHY. With the new architecture, bandwidth bottlenecks in next generation data center and communications infrastructures will be addressed.


In a release, Young Sohn, president and CEO of Inphi said, "Inphi continues to innovate. Our iPHY CMOS architecture is specifically designed to enable the development of next generation low power and small form factor 100 GbE transceivers. Together, working closely with leading OEMs and ecosystem partners, we can deliver more than 2X (News - Alert) reduction in power and size, and 10X increase in port density for 100 GbE transceivers versus existing solutions based upon silicon-germanium technology."

Sohn added that the mass transition from 10 GbE to 100 GbE in data center and communications infrastructures will be therefore accelerated.

The demand for increased/greater bandwidth of data center and service provider networks is expected to be addressed by the cost-effective, energy-efficient 100 GbE links. A path similar to that of the earlier Gigabit Ethernet and 10 GbE technologies is expected to be followed by 100 GbE. This growth will be supported with the evolution of the 100 GbE transceivers. For the growth of the 100 GbE, two critical steps however need to be taken care of.

The 100 GbE transceiver's high-speed SerDes needs to be migrated from its present implementation in exotic silicon-germanium technology to low power CMOS designs. The power consumption and size of the transceivers should be significantly reduced with introducing innovative architectures.

These steps will be addressed by the iPHY architecture. Comprehensive solutions for physical layer integrated circuits inside the transceiver module and on the line will be also offered. Over 2X reduction in transceiver power consumption and 10X increase in port density can be therefore achieved by the next generation 100 GbE systems. In the second half of 2011, Inphi expects to sample its first 100 GbE CMOS SerDes products.




Calvin Azuri is a contributing editor for TMCnet. To read more of Calvin’s articles, please visit his columnist page.

Edited by Jennifer Russell


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