Smart Data Centers Feature Editorial

Cypress Semiconductor Corp., a provider of static random access memories, announced that it has teamed up with TPACK to unveil a new reference design, called “Springbank,” for ultrafast Ethernet switches and queue management applications for traffic managers.

 

Offering an easy interface to various field-programmable gate arrays, the new Springbank reference design integrates TPACK’s (News - Alert) 40-Gbps carrier packet engine, TPX4004, with Cypress’s high-speed 65-nm 72-Mbit Quad Data Rate II+ (QDR II+) SRAMs, CY7C15632KV18.

 

Also backed by robust application support, the new reference design also provides the fastest available speeds with roadmaps for simple upgrades, according to officials with TPACK.

 

TPACK’s 40-Gbps TPX4004 carrier packet engine is a high-capacity integrated packet processor and traffic manager that provide true Metro Ethernet Forum (MEF (News - Alert))-defined, carrier-class performance. Due to its flexibility, this layer 2 switch provides the capability to adapt to different system architectures and requirements, say officials with TPACK.

 

According to Cypress, its CY7C15632KV18 72-Mbit QDRII+ SRAMs featured in the new reference design features clock speed of 550 MHz, market’s fastest available clock speed, and a total data rate of 80 Gbps in a 36-bit I/O width QDRII+ device, using half the power of 90-nm SRAMs. These QDRII+ SRAMs were the industry’s first to go into high-volume production on 65-nm line width.

 

The QDR II architecture of Cypress primarily encompasses two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.   

 

“Being first to market with this reference design demonstrates our technological leadership in high-throughput external memory solutions for carrier Ethernet switches and traffic managers,” said Thomas Rasmussen, VP of product line management at TPACK. “Partnering with Cypress assures us of the highest performance and reliability from the industry’s leading SRAM supplier.”

 

In addition, Cypress’s 65-nm QDR and DDR SRAMs lower input and output capacitance by nearly 60 percent when compared to their 90-nm predecessors. The company’s QDRII+ as well as DDRII+ devices features On-Die Termination (ODT) to enhance signal integrity, reduce system cost, and save board space by eliminating external termination resistors.

 

Officials with Cypress say that the 65-nm devices utilized in the new reference design makes use of an advanced design and technology that result in a 35 percent wider data valid window to reduce development time and cost for the customer.

 

“TPACK’s high-performance Springbank reference design is an excellent platform to showcase the blazing speeds of our 65-nm QDRII+ SRAMs in an advanced design for the networking market,” said David Kranzler, VP of synchronous memory and timing products at Cypress. “We look forward to working with TPACK on future projects, both with our SRAMS and our strong portfolio of timing solutions for networking applications.”